1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a transistor with SD extension regions and pocket regions, and more particularly to a method of manufacturing a semiconductor device having a transistor whose gate length is 0.18 xcexcm or less.
2. Description of the Related Art
Next-generation transistors whose gate length is 0.18 xcexcm or less are of a structure having SD extension regions and pocket regions, as shown in FIG. 1 of the accompanying drawings, for example, in order to increase an ON current for high-speed transistor operation and prevent a threshold voltage VTH from being lowered due to a known short channel effect.
The structure of an n-channel MOS (nMOS) transistor will be described below. A p-channel MOS (pMOS) transistor is basically of the same structure as such an n-channel MOS transistor except that a different impurity is injected.
As shown in FIG. 1, semiconductor substrate 1 has trenches of uniform depth filled with an oxide film (STI: Shallow Trench Isolation) as device separating regions 2 for separating transistors from each other. On semiconductor substrate 1, there are deposited gate insulating film 3 comprising an oxide nitride film, gate electrode 4 comprising a polysilicon film with phosphorus (P) or arsenic (As) injected therein, and a pair of side walls 5 disposed on opposite sides of gate electrode 4 for introducing ions at different rates into semiconductor substrate 1 to form SD extension regions and source/drain regions.
Semiconductor substrate 1 has source/drain regions 6 with arsenic (As) diffused therein in the vicinity of the surface thereof between device separating regions 2 of STI and side walls 5, and SD extension regions 7 disposed between ends of gate electrode 4 and ends of side walls 5 and containing an impurity (n type) at a density higher than source/drain regions 6. Semiconductor substrate 1 also has pocket regions 8 disposed near ends of source/drain regions 6 (near a channel), and containing an impurity (p type) at a density higher than semiconductor substrate 1 or a well region.
SD extension regions 7 have their impurity density higher than source/drain regions 6 for reducing the parasitic resistance of source/drain ends near the channel to increase the ON current. Since SD extension regions 7 intensify the short channel effect, however, pocket regions 8 having their impurity density higher than semiconductor substrate 1 or the well region are included to increase the impurity density on both channel ends thereby to prevent the threshold voltage VTH from being lowered. As shown in FIG. 1, the length of gate electrode 4 in the direction across the channel is generally referred to as gate length L, and the length between SD extension regions 7 as effective channel length Leff.
A method of manufacturing a semiconductor device having the transistor shown in FIG. 1 will be described below with reference to FIGS. 2A through 2I of the accompanying drawings. FIGS. 2A through 2I show successive steps of a typical fabrication process for transistors whose gate length is 0.13 xcexcm.
First, STI is formed in semiconductor substrate 1 according to a known process, thus forming device separating regions 2 for separating transistors.
Then, photoresist film 11 is deposited on semiconductor substrate 1 in a region other than a region where a pMOS transistor is to be formed, by photolithography. Then, phosphorus (P) is injected into the region where the pMOS transistor is to be formed under the conditions of 350 KeV and 2xc3x971013 atms/cm2, for example, to form an n well region (not shown), and arsenic (As) is further injected under the conditions of 100 KeV and 6xc3x971012 atms/cm2 to form a channel region (not shown) of the pMOS transistor (see FIG. 2A).
Then, photoresist film 12 is deposited on semiconductor substrate 1 in a region other than a region where an nMOS transistor is to be formed, by photolithography. Then, boron (B) is injected into the region where the nMOS transistor is to be formed under the conditions of 150 KeV and 2xc3x971013 atms/cm2, for example, to form a p well region (not shown), and boron is further injected under the conditions of 30 KeV and 2xc3x971012 atms/cm2 to form a channel region (not shown) of the nMOS transistor (see FIG. 2B).
Then, the surface of semiconductor substrate 1 is thermally oxidized and nitrided in a mixed atmosphere of nitrogen (N2) and oxygen (O2), growing gate insulating films 3 to a thickness of about 2.6 nm. A polysilicon film having a thickness of about 150 nm, which serves as gate electrodes 4, is deposited on gate insulating films 3 by CVD (Chemical Vapor Deposition). Thereafter, a photoresist film (not shown) is formed on the polysilicon film and patterned to a desired shape by photolithography. The polysilicon film is then etched away to form gate electrodes 4 (see FIG. 2C).
Then, photoresist film 13 is deposited on semiconductor substrate 1 in the region other than the region where the nMOS transistor is to be formed, by photolithography. Then, arsenic (As) is injected vertically into the region where the nMOS transistor is to be formed under the conditions of 2 KeV and 5xc3x971014 atms/cm2, for example, to form SD extension regions 7 of the nMOS transistor, and boron fluoride (BF2) is further injected rotationally (at about 30xc2x0 to the vertical direction) under the conditions of 30 KeV and 1.3xc3x971013 atms/cm2 to form pocket regions 8 of the nMOS transistor (see FIG. 2D).
Then, after the assembly is processed by an RTA (Rapid Thermal Anneal) process at 950xc2x0 C. for 10 sec. in a nitrogen atmosphere to eliminate point defects caused by the injection of arsenic (As) and boron fluoride (BF2), photoresist film 14 is deposited on semiconductor substrate 1 in the region other than the region where the pMOS transistor is to be formed, by photolithography. Then, boron fluoride (BF2) is injected vertically into the region where the pMOS transistor is to be formed under the conditions of 2.5 KeV and 5xc3x971014 atms/cm2, for example, to form SD extension regions 7 of the pMOS transistor, and arsenic (As) is further injected rotationally (at about 30xc2x0 to the vertical direction) under the conditions of 80 KeV and 1.5xc3x971013 atms/cm2 to form pocket regions 8 of the pMOS transistor (see FIG. 2E).
Then, an oxide film (TEOS-NSG) is grown to a thickness of about 70 nm on semiconductor substrate 1 in covering relation to gate electrodes 4 by a thermal CVD process, and then etched back by a dry etching process to form side walls 5 on both sides of gate electrodes 4.
Then, photoresist film 15 is deposited on semiconductor substrate 1 in the region other than the region where the pMOS transistor is to be formed, by photolithography. Using the gate electrode 4 as a mask in the region where the pMOS transistor is to be formed, boron (B) is injected vertically under the conditions of 3 KeV and 5xc3x971015 atms/cm2, for example, to form source/drain regions 6 of the pMOS transistor. In this ion implantation process, boron is also injected into gate electrode (polysilicon) 4 of the pMOS transistor (see FIG. 2F).
Then, photoresist film 16 is deposited on semiconductor substrate 1 in the region other than the region where the nMOS transistor is to be formed, by photolithography. Using the gate electrode 4 as a mask in the region where the nMOS transistor is to be formed, arsenic is injected vertically under the conditions of 30 KeV and 6xc3x971015 atms/cm2, for example, to form source/drain regions 6 of the pMOS transistor. In this ion implantation process, arsenic is also injected into gate electrode (polysilicon) 4 of the nMOS transistor (see FIG. 2G).
The dopants injected into source/drain regions 6 are activated by the RTA process at 1000xc2x0 C. for 10 sec. in a nitrogen atmosphere. Thereafter, a film of cobalt (Co) is deposited on gate electrodes 4 and source/drain regions 6 by a sputtering process, and thermally treated in a nitrogen atmosphere to grow cobalt silicide (CoSi2) film 17 to a thickness of about 35 nm (see FIG. 2H).
Then, a plasma oxide film is grown to a thickness of about 100 nm on semiconductor substrate 1 in covering relation to gate electrodes 4 by a plasma CVD process, and then a BPSG (Boro-Phospho-Silicate Glass) film is deposited on the plasma oxide film. Then, the surface of the BPSG film is planarized to produce interlayer insulating film 18 by a CMP (Chemical Mechanical Polishing) process.
A photoresist film (not shown) is selectively deposited on interlayer insulating film 18 by photolithography, and interlayer insulating film 18 in openings in the photoresist film are etched away, thus forming contact holes 19 by which source/drain regions 6 and upper surfaces of interlayer insulating film 18 will be interconnected.
A film of titanium (Ti), as a barrier metal, having a thickness of about 10 nm, or a film of titanium nitride (TiN), as a barrier metal, having a thickness of about 50 nm is deposited on the inner wall surfaces of contact holes 19, and brought into intimate contact with the inner wall surfaces of contact holes 19 by the RTA process at 690xc2x0 C. for 30 sec. Thereafter, a layer of tungsten (W), as an interconnection material, is embedded in contact holes 19 by the CVD process. Then, the surface of the assembly is planarized by the CMP process (see FIG. 2I). Thereafter, interconnections to source/drain regions 6 are formed according to a known process.
Modern semiconductor devices are suffering from the problem of dimensional variations posed by reduced transistor sizes that have resulted from highly integrated semiconductor device designs in recent years. Particularly problematic are variations in the gate dimensions that tend to greatly affect the transistor characteristics.
Gate electrodes may be produced with highly accurate dimensions using electron beams or X-rays having short wavelengths as exposure light sources. However, since exposure apparatus which employ electron beams or X-rays are expensive, they are responsible for an increase in the cost of semiconductor devices fabricated using those exposure apparatus.
For example, it is unavoidable to use electron beams or X-rays for fabricating smaller transistors whose gate length is 0.1 xcexcm or less. However, for the fabrication of larger transistors whose gate length L ranges from 0.1 to 0.18 xcexcm, it is preferable to use existing light sources such as exposure light sources, e.g., a KrF (Krypton-fluoride) laser, used to fabricate transistors whose gate length L is up to 0.25 xcexcm. Since the KrF laser beam has a wavelength of about 0.24 xcexcm, however, it necessarily causes gate dimension variations when used as an exposure light source for the fabrication of transistors whose gate length L is 0.18 xcexcm or shorter.
If a certain system is to be constructed of a plurality of types of semiconductor devices, then it needs to be designed in view of not only the average performance of the semiconductor devices but also possible worst characteristic variations thereof in order to achieve desired system capabilities. It therefore is highly important to uniformize the capabilities of the individual semiconductor devices.
One process of reducing such characteristic variations of the semiconductor devices is a feedback process which measures the characteristics of fabricated semiconductor devices of one lot to determine variations from design values and modify process parameters of process steps for a next lot of semiconductor devices in order to correct such variations.
However, such a feedback process is disadvantageous in that it is not immediately effective to correct variations from design values for the present lot of semiconductor devices. If gate length variations are caused for the reasons described above, then since the variations differ from lot to lot or from product to product, the process is not stable and the process parameters do not converge to desired values.
It is therefore an object of the present invention to provide a method of manufacturing a semiconductor device to achieve uniform transistor characteristics without changing circuit performance and reliability.
To achieve the above object, there is provided in accordance with the present invention a method of manufacturing a semiconductor device having a transistor with SD extension regions and pocket regions, comprising the steps of formulating the relationship between the difference between design and measured values of a gate length of a gate electrode of the transistor and a dose of an impurity to be injected into the SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values, measuring the gate length of the gate electrode which is produced by photolithography and etching process, and adjusting the dose of the impurity to be injected into the SD extension regions or the pocket regions to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship. In this method, since the characteristics of transistors of one lot can be brought closely to design values, it is possible to manufacture transistors of uniform characteristics which are not changed in circuit performance and reliability.
The dose of the impurity in the SD extension regions or the dose of the impurity in the pocket regions is used as a process parameter for adjustment. Therefore, the characteristics of the transistor can be brought closely to the design values without causing a change in the reliability of the transistor and the performance of a circuit that is composed of the transistor that has been adjusted.